Semiconductor memory devices such as random access memory (RAM) devices typically include a number of memory cells coupled to at least one bit line. The memory cells often include at least one storage device, storage node, and pass gate transistor. Generally, in a static random access memory (SRAM) cell, two storage devices such as drive transistors are coupled between two pass gate transistors, and a bit line is coupled to each of the pass gate transistors. Thus, each memory cell is often located between two bit lines.
The pass gate transistors (e.g., transfer gates) have gate electrodes which are coupled to word lines. A signal such as an address or select signal is provided on the word line associated with the memory cell to select or access a particular memory cell. Once the memory cell is selected via the word line, the memory cell can be read or written to through the pass gate transistors via the bit lines.
The memory cell of the SRAM often contains two inverters connected in anti-parallel. Basically, each cell is a flip-flop which has two stable states (e.g., a logic 1 or a logic 0). The memory cell is generally made of four or six transistors. In a four transistor SRAM cell, a first resistor is coupled in series with a first pull down (e.g., storage or drive) transistor at a first storage node, and a second resistor is coupled in series with a second pull down transistor at a second storage node. A first pass gate is coupled between a first bit line and the first storage node, and a second pass gate is coupled between a second bit line and a second storage node.
In a six transistor memory cell, the first and second resistors are replaced by first and second load transistors. The load transistors can be P-channel transistors or depletion mode N-channel transistors. The pull down transistors and pass gate transistors for both four transistor cells and six transistor cells are usually N-channel enhancement mode transistors.
As technology advances, memory cell size has steadily decreased so more memory cells can be located on a single semiconductor substrate. Additionally, power supply has decreased. The decreased memory cell size and power supply reduces the amount of charge stored at each of the storage nodes. The trend of decreasing charge storage per node makes the memory cell more susceptible to charge loss due to parasitic leakage problems.
Thus, there is a need for a memory cell with enhanced charge storage capacity. Further, there is a need for a memory cell of minimal size which can store and retain logic signals for an extended period of time. Further still, there is a need for a stable memory cell of small size which is relatively immune to noise and which does not require a significant number of additional fabrication steps.